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Verilog source code  |  1992-06-18  |  369 b   |  23 lines  |  [TEXT/MPS ]
  1. module regfile(clock, in_addr,   in,
  2.                       out1_addr, out1,
  3.                       out2_addr, out2);
  4.  
  5.     input            clock;
  6.     input      [31: 0]in;
  7.     input     [ 4: 0]in_addr,
  8.                     out1_addr,
  9.                     out2_addr;
  10.                 
  11.     output     [31: 0]out1,
  12.                     out2;
  13.                     
  14.     reg         [31: 0]r[32];
  15.     
  16.     assign     out1 = r[out1_addr];
  17.     
  18.     assign     out2 = r[out2_addr];
  19.     
  20.     always @(negedge clock)
  21.         r[in_addr] = in;
  22.                     
  23. endmodule